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Si4322
Data Filter Command
bit
15
1
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
al
6
ml
5
dsfi
4
sf
3
ewi
2
f2
1
f1
0
f0
POR
C462h
Bit 7 < al >:
Bit 6 < ml >:
Bit 5 < dsfi >:
Bit 4 < sf >:
Clock recovery (CR) auto lock control if set.
It means that the CR start in fast mode after locking it automatically switches to slow mode.
Clock recovery lock control
1: fast mode, fast attack and fast release - 0: slow mode, slow attack and slow release
Using the slower one requires more accurate bit timing (see Data Rate Command ).
Disables autosleep on FIFO interrupt if set to 1.
Selects the type of the data filter:
sf
0
1
Filter Type
Digital
Analog RC filter
Digital: this is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically
adjusted to the bit rate defined by the Data Rate Command .
Analog RC filter: the demodulator output is fed to the DCK pin over a 10 kOhm resistor. The filter characteristic is set by the external
capacitor connected to this pin and VSS. (Suggested value for 9600 bps is 1.8 nF).
Bit 3 < ewi >:
Bit 2-0 < f0:f2 >:
Enables the automatic wake-up on any interrupt event.
DQD threshold parameter.
Not e :
To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to
the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well.
Data Rate Command
bit
15
1
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
cs
6
r6
5
r5
4
r4
3
r3
2
r2
1
r1
0
r0
POR
C813h
The expected bit rate of the received data stream is determined by the 7-bit value R (bits r6 to r0 ) and the 1 bit cs .
BR = 10 MHz / 29 / (R+1) / ( 1 + cs *7)
In the receiver set R according the next function:
R= (10 MHz / 29 /( 1 + cs *7)/ BR) – 1
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
Clock recovery in slow mode: Δ BR/BR < 1/(29*N bit )
Clock recovery in fast mode: Δ BR/BR < 3/(29*N bit )
BR is the bit rate set in the receiver and Δ BR is bit rate difference between the transmitter and the receiver. N bit is the maximal number of
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and
be careful to use the same division ratio in the receiver and in the transmitter.
Δ BR is a theoretical limit for the clock recovery circuit. Clock recovery will not work above this limit. The clock recovery circuit will always
operate below this limit independently from process, temperature, or Vdd condition.
e.g. Supposing a maximum length of consecutive zeros or ones in the data stream is less than 5 bits, the necessary relative accuracy is
0.68% in slow mode and 2.1% in fast mode.
13
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